1. Field of the Invention
The field of the invention relates to the field of logic circuitry and in particular to the supply of power to logic circuitry in both functional and low power data retention modes.
2. Description of the Prior Art
It is known to provide power to logic circuitry using power rails connected via switch blocks to virtual power rails. The logic circuitry then draws its power from the virtual power rails. The switch blocks, which are typically high threshold voltage header and/or footer transistors, can be used to isolate the virtual power rail from the main power rail and accordingly isolate the logic blocks from the power supply and turn the circuitry off. This is useful in reducing power consumption of the logic circuitry. A problem with this is that state (e.g. data values, instruction values, configuration etc) within the logic circuitry is lost when it is isolated from the power supply. Furthermore, it can take a disadvantageously long period of time to restore this state and recommence processing using the logic circuitry when it is desired to switch out of the low power mode.
One way of at least partially addressing these problems is to provide balloon latches within the logic blocks to store relevant state signal values using circuits which do remain continuously powered (and are typically formed with high voltage threshold transistors having low leakage currents) so that the signal state values can be restored into the logic block when required and then processing recommenced. A problem with this approach is the overhead associated with the circuit area of the balloon latches, the control thereof and the time taken to restore the signal values from the balloon latches into the logic blocks.
Standby leakage current is becoming more of a problem on chips as the channel length continues to decrease on leading process nodes resulting in higher channel leakage. The dependence of standby leakage on supply voltage is a well known phenomena and a reduction of 15% in supply voltage can result in 50% reduction in leakage current. Since a modern microprocessor can have up to 2 billion transistors on the chip, the total standby leakage current contributes a significant amount to the power drain on the chip thereby impacting the overall energy efficiency of the system
Methods of adaptive power management or dynamic voltage scaling (DVS) in integrated circuits have been practiced for some years in the electronics industry to reduce the power dissipation on a chip. Adaptive power management becomes even more important with designs on leading edge nanometer technology where the leakage power is becoming as high as the dynamic power. The supply voltages have to be reduced with technology scaling to reduce dynamic power. However, a side effect of scaling is that these threshold voltages need to be lowered to prevent speed degradation which makes the transistors leakier. For example, for each 100 mV reduction in threshold voltage, the sub-threshold leakage current can increase by a factor of ten. Since mobile products are in standby mode most of the time, sometimes with variable standby operating times, an effective way of managing active leakage is by lowering the voltage of the logic when it is in a standby mode.
U.S. Pat. No. 7,737,720 assigned to the same applicant as this application provides a way of modulating (switching on and off repeatedly) the connection between the power supply, and the virtual power rail in order to control the voltage level of the virtual power rail to reduce power consumption within the integrated circuit.
U.S. application Ser. No. 12/591,017 assigned to the same applicant as this application discloses a power controller that selects the number of power control transistors which couples a virtual power rail to the power supply, so that the virtual power rail may be held at an intermediate voltage level and accordingly the power consumed by the logic circuitry can be reduced whilst the logic circuitry is supplied with sufficient power that retains its state.
It would be desirable to be able to reduce power consumption in standby mode, without losing data and without having an extended wake up time.